4:1 Multiplexer Dataflow Model in VHDL with truth table.

VHDL code for multiplexer using dataflow method – full code and explanation.

A multiplexer is a combinational logic circuit that has several inputs, on output and select lines. At any instant, only one of the input lines is connected to the output. The input line is chosen by the value of the select inputs. A general multiplexer is with n inputs, m select lines, and one output line is shown below.

Truth table of a 4:1 Mux

I0	I1	I2	I3	S0	S1	Y
I0	x	x	x	0	0	I0
x	I1	x	x	0	1	I1
x	x	I2	x	1	0	I2
x	x	x	I3	1	1	I3

VHDL code for multiplexer using dataflow method.

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX4_1 is
    Port ( i : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end MUX4_1;
architecture dataflow of MUX4_1 is
begin
with s select
y <=     i(0) when "00",
         i(1) when "01",
         i(2) when "10",
         i(3) when others;
end dataflow;